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silan semiconductors SC16232 hangzhou silan microelectronics joint-stock co.,ltd rev: 2.0 2002.04.26. 1 ram mapping 32 x 4 lcd controller for i/o c description the SC16232 is a 128 pattern(32x4), memory mapping, and multi- function lcd driver. the s/w configuration feature of the SC16232 makes it suitable for multiple lcd applications including lcd modules and display subsystems. only three or four lines are required for the interface between the host controller and the SC16232. the SC16232 contains a power down command to reduce power consumption. features * operating voltage: 2.4v ~ 5.2v * built-in 256khz rc oscillator * external 32.768khz crystal or 256khz frequency source input * selection of 1/2 or 1/3 bias, and selection of 1/2 or 1/3 or 1/4 duty lcd applications * internal time base frequency sources * two selectable buzzer frequencies(2khz/4khz) * power down command reduces power consumption * built-in time base generator and wdt * time base or wdt overflow output * 8 kinds of time base/wdt clock sources * 32x4 lcd driver * built-in 32x4 bit display ram * 3-wire serial interface * internal lcd driving frequency source chip topography ordering information device package SC16232 cob * software configuration feature * data mode and command mode instructions * r/w address auto increment * three data accessing modes * vlcd pin for adjusting lcd operating voltage
silan semiconductors SC16232 hangzhou silan microelectronics joint-stock co.,ltd rev: 2.0 2002.04.26. 2 pad assignment seg 0 seg 1 seg 2 data v ss osco v dd osci seg 3 seg 4 seg 5 seg 6 seg 8 seg 9 seg 10 seg 11 seg 12 seg 13 seg 14 seg 15 seg 7 seg 16 seg 17 seg 18 seg 19 seg 20 seg 21 seg 22 seg 23 seg 24 seg 25 seg 26 seg 27 seg 28 com2 com3 seg31 seg30 seg29 com0 com1 v lcd wr rd irq bz bz cs 1 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 2 3 4 5 6 7 8 9 12 13 14 15 16 17 18 19 32 31 30 29 28 27 26 25 24 23 22 21 20 11 SC16232 10 note: the ic substrate should be connected to v dd in the pcb layout artwork. block diagram 14 16 9 10 11 12 17 13 19 20 control and timing circuit tone frequency generator display ram lcd driver/ bias circuit 21 24 8 25 16 watchdog timer and time base generator 18 com0 com3 seg0 seg31 v lcd bz v ss v dd data osci osco cs rd wr bz irq notes: cs : chip selection ; bz, bz : tone outputs ; wr , rd , data: serial interface com0 ~ com3; seg) ~ seg31: lcd outputs ; irq : time base or wdt overflow output
silan semiconductors SC16232 hangzhou silan microelectronics joint-stock co.,ltd rev: 2.0 2002.04.26. 3 absolute maximum rating characteristic symbol value unit supply voltage v dd -0.3 ~ 5.5 v input voltage v in vss-0.3 ~ v dd +0.3 v storage temperature t stg -50 ~ +125 c operating temperature t opr -25~+75 c d.c. electrical characteristics (tamb=25 c , unless otherwise specified) test conditions parameter symbol v dd conditions min typ max unit operating voltage v dd -- -- 2.4 -- 5.2 v 3v -- 150 300 a i dd1 5v no load/lcd on on-chip rc oscillator -- 300 600 a 3v -- 60 120 a i dd2 5v no load/lcd on crystal oscillator -- 120 240 a 3v -- 100 200 a operating current i dd3 5v no load/lcd on external clock source -- 200 400 a 3v -- 0.1 5 a standby current i stb 5v no load power down mode -- 0.3 10 a 3v 0 -- 0.6 v input low voltage v il 5v data, wr , cs , rd 0--1.0v 3v 2.4 -- 3.0 v input high voltage v ih 5v data, wr , cs , rd 4.0 -- 5.0 v 3v v ol =0.3v 0.5 1.2 -- ma data, bz, bz , irq i ol1 5v v ol =0.5v 1.3 2.6 -- ma 3v v oh =2.7v -0.4 -0.8 -- ma data, bz, bz i oh1 5v v oh =4.5v -0.9 -1.8 -- ma 3v v ol =0.3v 80 150 -- a lcd common sink current i ol2 5v v ol =0.5v 150 250 -- a 3v v oh =2.7v -80 -120 -- a lcd common source current i oh2 5v v oh =4.5v -120 -200 -- a 3v v ol =0.3v 60 120 -- a lcd segment sink current i ol3 5v v ol =0.5v 120 200 -- a 3v v oh =2.7v -40 -70 -- a lcd segment source current i oh3 5v v oh =4.5v -70 -100 -- a 3v 40 80 150 k ? pull-high resistor r ph 5v data, wr , cs , rd 30 60 100 k ?
silan semiconductors SC16232 hangzhou silan microelectronics joint-stock co.,ltd rev: 2.0 2002.04.26. 4 a.c. electrical characteristics (tamb=25 c , unless otherwise specified) test conditions parameter symbol v dd conditions min typ max unit 3v -- 256 -- khz system clock f sys1 5v on-chip rc oscillator -- 256 -- khz 3v -- 32.768 -- khz system clock f sys2 5v crystal oscillator -- 32.768 -- khz 3v -- 256 -- khz system clock f sys3 5v external clock source -- 256 -- khz -- on-chip rc oscillator -- f sys1 /1024 -- hz -- crystal oscillator -- f sys2 /128 -- hz lcd clock f lcd -- external clock source -- f sys3 /1024 -- hz lcd common period t com -- n: number of com -- n/f lcd -- s 3v -- -- 150 khz serial data clock ( wr pin) f clk1 5v duty cycle 50% -- -- 300 khz 3v -- -- 75 khz serial data clock ( rd pin) f clk2 5v duty cycle 50% -- -- 150 khz tone frequency f tone -- on-chip rc oscillator -- 2.0 or 4.0 -- khz serial interface reset pulse width (figure 3) t cs -- cs -- 250 -- ns write mode 3.34 -- -- 3v read mode 6.67 -- -- s write mode 1.67 -- -- wr , rd input pulse width (figure 1) t clk 5v read mode 3.34 -- -- s 3v rise/fall time serial data clock width (figure 1) t r ,t f 5v -- -- 120 -- ns 3v setuptimefordatato wr , rd clock width (figure 2) t su 5v -- -- 120 -- ns 3v hold time for data to wr , rd clock width (figure 2) t h 5v -- -- 120 -- ns 3v setuptimefor cs to wr , rd clock width (figure 3) t su1 5v -- -- 100 -- ns 3v hold time for cs to wr , rd clock width (figure 3) t h1 5v -- -- 100 -- ns
silan semiconductors SC16232 hangzhou silan microelectronics joint-stock co.,ltd rev: 2.0 2002.04.26. 5 wr,rd clock 90% 50% 10% t f t r t clk t clk v dd gnd figure 1 50% gnd v dc gnd v dc clock wr,rd db valid data 50% t h t sl figure 2 50% cs wr,rd clock 50% last clock first clock gnd v dc gnd v dc t cs t h1 t su1 figure 3 pad description pad no. symbol i/o description 1 cs i chip selection input with pull-high resistor. when the cs is logic high, the data and command read from or written to the SC16232 are disabled. the serial interface circuit is also reset. but if cs is at logic low level and is input to the cs pad, the data and command transmission between the host controller and the SC16232 are all enabled. 2 rd i read clock input with pull-high resistor. data in the ram of the SC16232 are clocked out on the falling edge of the rd signal. the clocked out data will appear on the data line. the host controller can use the next rising edge to latch the clocked out data. (to be continued)
silan semiconductors SC16232 hangzhou silan microelectronics joint-stock co.,ltd rev: 2.0 2002.04.26. 6 pad description (continued) pad no. symbol i/o description 3 wr i write clock input with pull-high resistor. data on the data line are latched into the SC16232 on the rising edge of the wr signal. 4 data i/o serial data input/output with pull-high resistor. 5v ss -- negative power supply, gnd. 7oscii 6oscoo the osci and osco pads are connected to a 32.768khz crystal in order to generate a system clock. if the system clock comes from an external clock source, the external clock source should be connected to the osci pad. but if an on-chip rc oscillator is selected instead, the osci and osco pads can be left open, 8v lcd i lcd power supply. 9v dd -- positive power supply. 10 irq o time base or wdt overflow flag, nmos open drain output. 11,12 bz, bz o 2khz or 4khz tone frequency output pair. 13 ~16 com0 ~ com3 o lcd common outputs. 48 ~17 seg0 ~ seg31 o lcd segment outputs. functional description 1. display memory ? ram the static display memory(ram) is organized into 32x4 bits and stores the displayed data. the contents of the ram are directly mapped to the contents of the lcd driver. data in the ram can be accessed by the read, write and read-modify-write commands. the following is a mapping from the ram to the lcd pattern: com3 com2 com1 com0 seg0 0 seg1 1 seg2 2 seg3 3 seg31 31 d3 d2 d1 d0 addr data address 6 bits (a5,a4,?,a0) data 4 bits (d3,d2,d1,d0) ram mapping
silan semiconductors SC16232 hangzhou silan microelectronics joint-stock co.,ltd rev: 2.0 2002.04.26. 7 2. system oscillator the SC16232 system clock is used to generate the time base/watchdog timer(wdt) clock frequency, lcd driving clock, and tone frequency. the source of the clock may be from an on-chip rc oscillator(256 khz), a crystal oscillator(32.768 khz), or an external 256khz clock by the s/w setting. the configuration of the system oscillator is as shown. after the sys dis command is executed, the system clock will stop and the lcd bias generator will turn off. that command is, however, available only for the on-chip rc oscillator or for the crystal oscillator. once the system clock stops, the lcd display will become blank, and the time base/wdt lose its function as well. the lcd off command is used to turn the lcd bias generator off. after the lcd bias generator switches off by issuing the lcd off command, using the sys dis command reduces power consumption, serving as a system power down command. but if the external clock source is chosen as the system clock, using the sys dis command can neither turn the oscillator off nor carry out the power down mode. the crystal oscillator option can be applied to connect an external frequency source of 32khz to the osci pin. in this case, the system fails to enter the power down mode, similar to the case in the external 256khz clock source operation. at the initial system power on, the SC16232 is at the sys dis state. crystal oscillator 32768hz extemal clock source 256khz on-chip rc oscillator 256khz 1/8 osco osci system clock system oscillator configuration 3. time base and watchdog timer (wdt) the time base generator is comprised by an 8-stage count-up ripple counter and is designed to generate an accurate time base. the watch dog timer (wdt), on the other hand, is composed of an 8-stage time base generator along with a 2-stage count-up counter, and is designed to break the host controller or other subsystems from abnormal states such as unknown or unwanted jump, execution errors, etc. the wdt time-out will result in the setting of an internal wdt time-out flag. the outputs of the time base generator and of the wdt time-out flag can be connected to the irq output by a command option. there are totally eight frequency sources available for the time base generator and the wdt clock. the frequency is calculated by the following equation. f wdt= n 2 32khz
silan semiconductors SC16232 hangzhou silan microelectronics joint-stock co.,ltd rev: 2.0 2002.04.26. 8 where the value of n ranges from 0 to 7 by command options. the 32khz in the above equation indicates that the source of the system frequency is derived from a crystal oscillator of 32.768khz, an on-chip oscillator(256khz), or an external frequency of 256khz. if an on-chip oscillator(256khz) or an external 256khz frequency is chosen as the source of the system frequency, the frequency source is by default prescaled to 32khz by a 3-stage prescaler. employing both the time base generator and the wdt related commands, one should be careful since the time base generator and wdt share the same 8-stage counter. for example, invoking the wdt dis command disables the time base generator whereas executing the wdt en command not only enables the time base generator but activates the wdt time-out flag output (connect the wdt time-out flag to the irq pin). after the timer en command is transferred, the wdt is disconnected from the irq pin, and the output of the time base generator is connected to the irq pin. the wdt can be cleared by executing the clr wdt command, and the contents of the time base generator is cleared by executing the clr wdt or clr timer command. the clr wdt or the clr timer command should be executed prior to the wdt en or the timer en command respectively. before executing the irq en command the clr wdt or clr timer command should be executed first. the clr timer command has to be executed before switching from the wdt mode to the time base mode. once the wdt time-out occurs, the irq pin will stay at a logic low level until the clr wdt or the irq dis command is issued. after the irq output is disable the irq pin will remain at the floating state. the irq output can be enabled or disabled by executing the irq en or the irq dis command, respectively. the irq en makes the output of the time base generator or of the wdt time-out flag appear on the irq pin. the configuration of the time base generator along with the wdt are as shown. in the case of on-chip rc oscillator or crystal oscillator, the power down mode can reduce power consumption since the oscillator can be turned on or off by the corresponding system commands. at the power down mode the time base/wdt loses all its functions. on the other hand, if an external clock is selected as the source of system frequency the sys dis command turns out invalid and the power down mode fails to be carried out. that is, after the external clock source is selected, the SC16232 will continue working until system power fails or the external clock source is removed. after the system power on, the irq will be disabled. timer/wdt clock sources / 2 n n=0 ~ 7 / 256 /4 v dd r ck dq timer en/dis wdt en/dis irq en/dis irq clr wdt system clock f=32khz timer and wdt configuration
silan semiconductors SC16232 hangzhou silan microelectronics joint-stock co.,ltd rev: 2.0 2002.04.26. 9 4. tone output a simple tone generator is implemented in the SC16232. the tone generator can output a pair of differential driving signals on the bz and bz , which are used to generate a single tone. by executing the tone4k and tone2k commands there are two tone frequency outputs selectable. the tone4k and tone2k commands set the tone frequency to 4khz and 2khz, respectively. the tone output can be turned on or off by invoking the tone on or the tone off command. the tone outputs, namely bz and bz , are a pair of differential driving outputs used to drive a piezo buzzer. once the system is disabled or the tone output is inhibited, the bz and the bz outputs will remain at low level. 5. lcd driver the SC16232 is a 128(32x4) pattern lcd driver. it can be configured as 1/2 or 1/3 bias and 2 or 3 or 4 commons of lcd driver by the s/w configuration. this feature makes the SC16232 suitable for multiply lcd applications. the lcd driving clock is derived from the system clock. the value of the driving clock is always 256hz even when it is at a 32.768khz crystal oscillator frequency, an on-chip rc oscillator frequency, or an external frequency. the lcd corresponding commands are summarized in the table below. name command code function lcd off 100 00000010x turn off lcd outputs lcd on 100 00000011x turn on lcd outputs bias & com 100 0010abxcx c=0: 1/2 bias option c=1: 1/3 bias option ab=00: 2 commons option ab=01: 3 commons option ab=10: 4 commons option the bold form of 1 0 0, namely 100 , indicates the command mode id. if successive commands have been issued, the command mode id except for the first command, will be omitted. the lcd off command turns the lcd display off by disabling the lcd bias generator. the lcd on command, on the other hand, turns the lcd display on by enabling the lcd bias generator. the bias and com are the lcd panel related commands. using the lcd related commands, the SC16232 can be compatible with most types of lcd panels.
silan semiconductors SC16232 hangzhou silan microelectronics joint-stock co.,ltd rev: 2.0 2002.04.26. 10 6.command format the SC16232 can be configured by the s/w setting. there are two mode commands to configure the SC16232 resources and to transfer the lcd display data. the configuration mode of the SC16232 is called command mode, and its command mode id is 100 . the command mode consists of a system configuration command, a system frequency selection command, a lcd configuration command, a tone frequency selection command, a timer/wdt setting command, and an operating command. the data mode, on the other hand, includes read, write, and read-modify-write operations. the following are the data mode ids and the command mode id: operation mode id read data 1 1 0 write data 101 read-modify-write data 1 0 1 command command 1 0 0 the mode command should be issued before the data or command is transferred. if successive commands have been issued, the command mode id, namely 100 , can be omitted. while the system is operating in the non- successive command or the non-successive address data mode, the cs pin should be set to ?1? and the previous operation mode will be reset also. once the cs pin returns to ?0?, a new operation mode id should be issued first. 7. interfacing only four lines are required to interface with the SC16232. the cs line is used to initialize the serial interface circuit and to terminate the communication between the host controller and the SC16232. if the cs pin is set to 1, the data and command issued between the host controller and the SC16232 are first disabled and then initialized. before issuing a mode command or mode switching, a high level pulse is required to initialize the serial interface of the SC16232. the data line is the serial data input/output line. data to be read or written or commands to be writtenhavetobepassedthroughthedataline.the rd line is the read clock input. data in the ram are clocked out on the falling edge of the rd signal, and the clocked out data will then appear on the data line. it is recommended that the host controller read in correct data during the interval between the rising edge and the next falling edge of the rd signal. the wr line is the write clock input. the data, address, and command on the data line are all clocked into the SC16232 on the rising edge of the wr signal. there is an optional irq line to be used as an interface between the host controller and the SC16232. the irq pin can be selected as a timer output or a wdt overflow flag output by the s/w setting. the host controller can perform the time base or the wdt function by being connected with the irq pin of the SC16232.
silan semiconductors SC16232 hangzhou silan microelectronics joint-stock co.,ltd rev: 2.0 2002.04.26. 11 timing diagrams read mode (command code : 1 1 0) cs wr rd data memory address 1 (ma1) data(ma1) memory address 2 (ma2) data(ma2) 0 1 1 a5 a4 a3 a1 a2 a0 d0 d1 d2 d3 1 1 0 a5 a4 a3 a1 a2 a0 d0 d1 d2 d3 read mode (successive address reading) 1 1 0 a4 a3 a2 a1 a0 d0 d1 d2 d3 d0 d1 d2 d3 d0 d1 d2 d3 d0 d1 d2 d3 d0 a5 cs wr rd data memory address (ma) data (ma) data (ma+1) data (ma+2) data (ma+3)
silan semiconductors SC16232 hangzhou silan microelectronics joint-stock co.,ltd rev: 2.0 2002.04.26. 12 timing diagrams (continued) write mode (command code : 1 0 1) cs wr data 0 1 a5 a4 a3 a2 a1 a0 d0 d1 d2 d3 0 1 1 a5 a4 a3 a2 a1 a0 d0 d1 d2 d3 1 memory address 2(ma2) data (ma1) data (ma2) memory address 1(ma1) write mode (successive address writing) cs wr data 0 1 a5 a4 a3 a2 a1 a0 d0 d1 d2 d3 d2 d1 d3 d0 d1 d2 d3 d0 d1 d2 d3 d0 1 memory address (ma) data (ma) data (ma+3) d0 data (ma+1) data (ma+2)
silan semiconductors SC16232 hangzhou silan microelectronics joint-stock co.,ltd rev: 2.0 2002.04.26. 13 timing diagrams (continued) read-modify-write mode (command code : 1 0 1) 1 0 1 a5 a4 a3 a2 a1 a0 d0 d1 d2 d3 d0 d1 d2 d3 1 0 1 a4 a3 a2 a1 a0 d0 d1 d2 d3 a5 data cs rd wr memory address(ma1) data(ma1) data(ma1) memory address(ma2) data(ma2) read-modify-write mode (successive address accessing) 1 0 1 a5a4a3a2a1a0d0d1d2d3d0d1d2d3d0d1d2d3d0d1d2d3d0d1d2d3d0 memory address(ma) data (ma) data (ma) data (ma+1) data (ma+1) data (ma+2) data rd wr cs
silan semiconductors SC16232 hangzhou silan microelectronics joint-stock co.,ltd rev: 2.0 2002.04.26. 14 timing diagrams (continued) command mode (command code : 1 0 0) 1 0 0 c8c7c6c5 c8 c3c2c1c0 c4 c3 c2 c1 c0 c7 c6 c5 c4 command 1 command or data mode command ... command i data cs wr mode (data and command mode) data cs wr rd command or data mode address &data command or data mode address &data address &data command or data mode note: it is recommended that the host controller should read in the data from the data line between the rising edge of the rd line and the falling edge of the next rd line.
silan semiconductors SC16232 hangzhou silan microelectronics joint-stock co.,ltd rev: 2.0 2002.04.26. 15 typical application circuits SC16232 9 10 11 12 18 16 14 21 24 8 25 20 19 17 16 c *r external clock 1 external clock 2 on-chip osc crystal 32768hz clock out data osci osco cs rd wr irq com0 ~ com3 seg0 ~ seg31 bz bz v lcd v dd lcd panel piezo vr 1/2 or 1/3 bias; 1/2,1/3 or 1/4 duty notes: the connection of irq and rd pin can be selected depending on the requirement of the c. the voltage applied to v lcd pin must be lower than v dd . adjust v r to fit lcd display, at v dd =5v, v lcd =4v,vr=15k ? 20%, adjust r(external pull-high resistance) to fit user?s time base clock.
silan semiconductors SC16232 hangzhou silan microelectronics joint-stock co.,ltd rev: 2.0 2002.04.26. 16 command summary name id command code d/c function def. read 110 a5a4a3a2a1a0d0d1d2d3 d read data from the ram write 101 a5a4a3a2a1a0d0d1d2d3 d write data to the ram read-modify-write 101 a5a4a3a2a1a0d0d1d2d3 d read and write to the ram sys dis 100 0000-0000-x c turn off both system oscillator and lcd bias generator yes sys en 100 0000-0001-x c turn on system oscillator lcd off 100 0000-0010-x c turn off lcd bias generator yes lcd on 100 0000-0011-x c turn on lcd bias generator timer dis 100 0000-0100-x c disable time base output wdt dis 100 0000-0101-x c disable wdt time-out flag output timer en 100 0000-0110-x c enable time base output wdt en 100 0000-0111-x c enable wdt time-out flag output tone off 100 0000-1000-x c turn off tone outputs yes tone on 100 0000-1001-x c turn on tone outputs clr timer 100 0000-11xx-x c clear the contents of time base generator clr wdr 100 0000-111x-x c clear the contents of wdt stage xtal 32k 100 0001-01xx-x c system clock source, crystal oscillator rc 256k 100 0001-10xx-x c system clock source, on-chip rc oscillator yes ext 256k 100 0001-11xx-x c system clock source, external clock source bias 1/2 100 0010-abx0-x c lcd 1/2 bias option ab=00:2 commons option ab=01:3 commons option ab=10:4 commons option bias 1/3 100 0010-abx1-x c lcd 1/3 bias option ab=00:2 commons option ab=01:3 commons option ab=10:4 commons option tone 4k 100 010x- xxxx-x c tone fr equency, 4khz tone 2k 100 011x- xxxx-x c tone fr equency, 2khz irq dis 100 100x-0 xxx-x c disable irq output yes (to be continued)
silan semiconductors SC16232 hangzhou silan microelectronics joint-stock co.,ltd rev: 2.0 2002.04.26. 17 command summary (continued) name id command code d/c function def. irq en 100 100x-1 xxx-x c enable irq output f1 100 101x-x000-x c time base/wdt clock output: 1hz the wdt time-out flag after: 4s f2 100 101x-x001-x c time base/wdt clock output: 2hz the wdt time-out flag after: 2s f4 100 101x-x010-x c time base/wdt clock output: 4hz the wdt time-out flag after:1s f8 100 101x-x011-x c time base/wdt clock output: 8hz the wdt time-out flag after:1/2s f16 100 101x-x100-x c time base/wdt clock output: 16hz the wdt time-out flag after:1/4s f32 100 101x-x101-x c time base/wdt clock output: 32hz the wdt time-out flag after:1/8s f64 100 101x-x110-x c time base/wdt clock output: 64hz the wdt time-out flag after:1/16s f128 100 101x-x111-x c time base/wdt clock output: 128hz the wdt time-out flag after:1/32s yes topt 100 1110-0000-x c test mode tnormal 100 1110-0011-x c normal mode yes notes: x: don?t care, a5 ~ a0: ram addresses, d3 ~ d0: ram data, d/c: data/command mode, def.: power on reset default. all the bold forms, namely 110 , 101 , and 100 , are mode commands. of these, 100 indicates the command mode id. if successive command have been issued, the command mode id except for the first command will be omitted. the source of the tone frequency and of the time base/wdt clock frequency can be derived from an on-chip 256khz rc oscillator, a 32,768khz crystal oscillator, or an external 256khz clock. calculation of the frequency is based on the system frequency sources as stated above. it is recommended that the host controller should initialize the SC16232 after power on reset, for power on reset may fail, which in turn leads to the malfunctioning of the SC16232.
silan semiconductors SC16232 hangzhou silan microelectronics joint-stock co.,ltd rev: 2.0 2002.04.26. 18 chip topography 48 1 47 46 45 44 43 42 41 40 39 38 37 36 35 34 32 30 31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 6 5 4 2 33 3 7 chip size: 2.25 x 2.42(mm 2 )
silan semiconductors SC16232 hangzhou silan microelectronics joint-stock co.,ltd rev: 2.0 2002.04.26. 19 pad coordinates (unit: m) pad no. x y pad no. x y 1 -1000 -1080 25 300 1080 2 -320 -1080 26 150 1080 3 -190 -1080 27 15 1080 4 -60 -1080 28 -125 1080 5 70 -1080 29 -265 1080 6 200 -1080 30 -405 1080 7 575 -1080 31 -545 1080 8 705 -1080 32 -685 1080 9 835 -1080 33 -1000 1080 10 1000 -1080 34 -1000 945 11 1000 -865 35 -1000 810 12 1000 -670 36 -1000 675 13 1000 -530 37 -1000 540 14 1000 -400 38 -1000 405 15 1000 -270 39 -1000 270 16 1000 -140 40 -1000 135 17 1000 -10 41 -1000 0 18 1000 120 42 -1000 -135 19 1000 250 43 -1000 -270 20 995 1080 44 -1000 -405 21 855 1080 45 -1000 -540 22 715 1080 46 -1000 -675 23 575 1080 47 -1000 -810 24 435 1080 48 -1000 -945 note: the original point of the coordinate is the die center.
silan semiconductors SC16232 hangzhou silan microelectronics joint-stock co.,ltd rev: 2.0 2002.04.26. 20 attach revision history data rev description page 2000.12.31 1.0 original 2002.04.26 2.0 add the ? ordering information? the ?sc1621? change to ?SC16232? 1

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